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I am using the External Memory Interface IP core in Qsys to connect to a DDR3 daughter memory card through the Arria 10 GX FPGA Development Kit via the HiLo interface. I am also using an address span extender between the CPU and EMI the connects to the EMI's ctrl_amm_0 port; there is an error claming that the data width of this connection must be of power of two and between 8 and 4096. I'm not sure how to check the current data width or what I need to change to get the size to a power of two.
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I had the same issue in Qsys and resolved it by regenerating the EMIF core wtih a DQ width of 64 (8 pins per DQS group) instead of the 72 that is supported on my board. I was able to generate the core outside of Qsys using the IP Parameter Editor though without any problems.
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