I have a board we developed using an Arria10 and DDR4. Our project uses the HPS EMIF interface. But I created a standalone version and the operation appears to be the same. The EMIF interface is reporting calibration failure and the EMIF toolkit reports appear to fail at a catastrophic level. The signals output from the standalone EMIF indicate the PLL is locked, and the cal fail is active. I have recorded the power up reset and init sequence in a series of scope captures and tables. The first thing that seems incorrect - is a sequence of 11 reset pulses right at the start (and every time I issue the command "Rerun calibration" from the toolkit). The second is I cannot find any indication that the memory interface is commanding any periodic refresh (CKE never triggers and CS_n never triggers). I have some files that I have created to provide the data I have assembled regarding the measurements of the power up reset and initialization sequence of the DDR4, but I would like to send them privately instead of on the public domain for company proprietary reasons. Please let me know how I can provide the data. Thank you!

So you say that you've taken the HPS out of the equation by creating a standalone design, which is good. But is the standalone design your own design or are you generating the example design project from the EMIF IP parameter editor and using that design straight with no alteration (other than assigning to the appropriate I/O banks to connect to the external memory)? If it's not the example design, try the example design first and see if you're getting the same results. If it is the example design and you're still running into issues, a good sanity check is to check your parameter settings one by one against the external memory requirements from the external devices specifications. It may seem tedious, but there are so many settings, it's very easy to make a mistake that prevents even basic operation of the interface.

Hi - thanks for the response. Yes - I made the example design from the EMIF parameter editor. And yes, I have already gone one by one through the memory timing compared to the datasheet.

Hi CKE and CS_n never toggle is bit strange. How about memory clock ? Memory clock should toggle all the time regards of calibration fail.

Thank you for the response! Yes, once the Clock (CK_t and CK_c) becomes active in the reset and init sequence, they stay active indefinitely. Clarification regarding CKE and CS_n - I do see activity on these signals at power up and when I execute the "Rerun Calibration" command. But only then. If I just let the board sit powered on and do not initiate any commands, neither of these signals toggle at all. Also - in the EMIF Toolkit Calibration Report, the VREFIN level looks like it is 1.10V - Is this correct? I would think it should be 0.6V.

Hi I think that reason of CKE and CS_n does not toggle after rerun calibration is calibration is failing. If the calibration passed the EMIF controller is open to the user interface , but the case of calibration is falling EMIF controller is closed to user interface. For the VrefIN the voltage should be 0.6V as you mentioned.

Arria 10 DDR4 EMIF IP Calibration Failure

17 Replies

sstrell
Super Contributor
5 years ago
So you say that you've taken the HPS out of the equation by creating a standalone design, which is good. But is the standalone design your own design or are you generating the example design project from the EMIF IP parameter editor and using that design straight with no alteration (other than assigning to the appropriate I/O banks to connect to the external memory)? If it's not the example design, try the example design first and see if you're getting the same results.

If it is the example design and you're still running into issues, a good sanity check is to check your parameter settings one by one against the external memory requirements from the external devices specifications. It may seem tedious, but there are so many settings, it's very easy to make a mistake that prevents even basic operation of the interface.
- JHenk3
  Occasional Contributor
  5 years ago
  Hi - thanks for the response.
  
  Yes - I made the example design from the EMIF parameter editor.
  
  And yes, I have already gone one by one through the memory timing compared to the datasheet.
yoichiK_altera
Contributor
5 years ago
Hi

CKE and CS_n never toggle is bit strange. How about memory clock ? Memory clock should toggle all the time regards of calibration fail.
- JHenk3
  Occasional Contributor
  5 years ago
  Thank you for the response!
  
  Yes, once the Clock (CK_t and CK_c) becomes active in the reset and init sequence, they stay active indefinitely.
  
  Clarification regarding CKE and CS_n - I do see activity on these signals at power up and when I execute the "Rerun Calibration" command. But only then. If I just let the board sit powered on and do not initiate any commands, neither of these signals toggle at all.
  
  Also - in the EMIF Toolkit Calibration Report, the VREFIN level looks like it is 1.10V - Is this correct? I would think it should be 0.6V.
  - yoichiK_altera
    Contributor
    5 years ago
    Hi
    
    I think that reason of CKE and CS_n does not toggle after rerun calibration is calibration is failing.
    
    If the calibration passed the EMIF controller is open to the user interface , but the case of calibration is falling EMIF controller is closed to user interface.
    
    For the VrefIN the voltage should be 0.6V as you mentioned.

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Arria 10 DDR4 EMIF IP Calibration Failure

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