Occasional Contributor
Occasional ContributorThank you for the response!
Yes, once the Clock (CK_t and CK_c) becomes active in the reset and init sequence, they stay active indefinitely.
Clarification regarding CKE and CS_n - I do see activity on these signals at power up and when I execute the "Rerun Calibration" command. But only then. If I just let the board sit powered on and do not initiate any commands, neither of these signals toggle at all.
Also - in the EMIF Toolkit Calibration Report, the VREFIN level looks like it is 1.10V - Is this correct? I would think it should be 0.6V.
ContributorHi
I think that reason of CKE and CS_n does not toggle after rerun calibration is calibration is failing.
If the calibration passed the EMIF controller is open to the user interface , but the case of calibration is falling EMIF controller is closed to user interface.
For the VrefIN the voltage should be 0.6V as you mentioned.
Occasional ContributorOk, if the EMIF report is saying that VREFIN is 1.1 and the via at VREFCA is measuring at 0.6V on all three DDR4 components, then what could be happening in the IP or the EMIF GUI that indicates a different value?
ContributorHi
Arria10 DDR4 EMIF IP use the internal VREF for DDR4 interface. I presume that Device generates the Vref internally and EMIF GUI reports that Vref number. I am not sure why the 1.1v is generated for Vref.
ContributorHi
Can you attach stand along design and board schematic ?
then I can check quick check on that.
