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Aflop's avatar
Aflop
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9 months ago
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Arria 10 - PCIe Hard IP - 2x PCIe Gen3x8 OR 1xPCIe Gen3x16

My company produced a custom board with an Arria 10 FPGA and a PCIe Gen3x16 interface. While looking at the specifications for the "Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP" we found that...
  • VenT_Altera's avatar
    9 months ago

    Hi Aflop,


    "1 IP for the first 8 channels and another IP for the next 8 channels"

    I think it depends on whether the 16 channels (RX and TX signals) in the FPGA are from the same bank.

    1. If they are from the same bank, you can only instantiate 1 PCIe IP even though the next 8 channels (in the case of Gen3 x8) are unused. This results in 1 PCIe device.

    2. If they are from the same bank, you can instantiate 1 PCIe IP and perform PCIe bifurcation Gen3 2x8, allowing it to work as two separate PCIe devices. However, this requires the PCIe IP to support PCIe bifurcation. In your case, unfortunately, Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express does not have support to PCIe bifurcation. https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/features.html

    3. On the other hand, if they are from a separate bank, and you instantiate 2 Gen3 x8 PCIe IP, I think the one endpoint hardware can be recognized and enumerated by the host as two separate PCIe endpoint devices.


    Thanks.

    Best Regards,

    Ven