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Altera_Forum's avatar
Altera_Forum
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17 years ago

Area Optimized FFT hardware design

Hi,

I'm developing my own custom hardware design of FFT algorithm (radix-2, CORDIC based), the design is resources constrained, with certain timing requirements to be met (timing constraints are relaxed).

Now, I want to evaluate my design versus other area optimized reference designs. I searched in Altera reference designs library, but the FFT design there is balanced between time and area optimization, however what I'm looking for is a purely resources optimized design to have fair evaluation of my design.

Anybody can help?

Thanks in advance.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thanks a lot for this useful information, it really helped me.

    However, it'd be more helpful if the FPGA utilization was mentioned in the results in addition to multipliers, adders and memory usage results. It's mentioned in the paper that VHDL simulations were held for those algorithms, but no mention of the actual resources usage of the FPGA. Actually FPGA usage is a very important evaluation point in my study, since i'm not developing an algorithm as much as i'm implementing it on hardware.

    Also, I'm making a similar study on DCT processor (based on CORDIC too), so do u know similar area optimized design to compare to, like the ones u mentioned for FFT?