Area Optimized FFT hardware design

Thanks a lot for this useful information, it really helped me.

However, it'd be more helpful if the FPGA utilization was mentioned in the results in addition to multipliers, adders and memory usage results. It's mentioned in the paper that VHDL simulations were held for those algorithms, but no mention of the actual resources usage of the FPGA. Actually FPGA usage is a very important evaluation point in my study, since i'm not developing an algorithm as much as i'm implementing it on hardware.

Also, I'm making a similar study on DCT processor (based on CORDIC too), so do u know similar area optimized design to compare to, like the ones u mentioned for FFT?