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New ContributorApparent error in Agilex DDR4 EMIF IP model - "maximumPendingReadTransactions" is "1"
Hello!
The Agilex DDR4 EMIF IP model for Platform Designer (qpro20.4.0.72) appears to have an error in the AvMM parameters, namely, that the “maximumPendingReadTransactions” parameter is set to “1” (see attached screen capture). I have run the DDR4 EMIF example design simulation, and can see that the parameter should be at least 16, as I can see that the EMIF accepts at least 16 outstanding reads during that simulation.
The AvMM spec has this to say about this case of accepting more reads than indicated by “maximumPendingReadTransactions” :
If a slave interface accepts more read transfers than allowed, the interconnect pending read FIFO may overflow with unpredictable results. The slave may lose readdata or route readdata to the wrong master interface. Or, the system may lock up. The slave interface must assert waitrequest to prevent this overflow.
The effect of this is that in the AvMM interconnect in our design, Platform Designer is only making the “agent_rsp_fifo” 2 deep, but has enabled FIFO overflow protection. My understanding is that the interconnect will therefore throttle the AvMM masters, including writes, after the EMIF slave accepts 2 reads (one more than is “legal” for its "maximumPendingReadTransactions”).
While this should “work” as far as functionality is concerned, it will not “work" for our application, as more than 2 outstanding reads are required to achieve the required read bandwidth from DDR. Furthermore, blocking all writes with only 2 reads are outstanding will throttle performance on the write side, as well.
As an experiment, I changed the “maximumPendingReadTransactions” parameter in the relevant places in the .qsys and .ip files, and regenerated the RTL in Platform Designer. In that case the “agent_rsp_fifo” was changed to 17 deep, which confirms that the incorrect value for that parameter is the problem.
Thanks!
