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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

API calls failed while running PCIe DMA transfer example design

Hi,

I was working the PCIe DMA transfer example design for Arria 10. I have added a counter custom IP which counts upto 1000, and An Avalon FIFO IP with the design. My intention is to write the data created in counter to DDR4 and then use the DMA API call (provided by Terasic in Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp) to read them from PC.

Even if I follows the steps given in the User manual of DE5a_DDR4_NET (attaching the manual. The chapter-7 section 7.6 is what I was following), the DMA API calls to read data fails. I would like to know why I could not run Read DMA API from the PC.

The It would be great if someone could give any helping hand. I am attaching the error message (Crash_op.PNG).

I am just listing the procedure I followed,

1. Installed both DDR4 2400 4GB SODIMM on the FPGA board.

2. Connected the FPGA board with PC through PCIe.

3. Configured FPGA with DE5A_NET.sof (here the design .sof having PCIe DMA transfer example design + Avalon FIFO + Counter custom IP) by executing the test.bat.

4. Restart Windows

4. I could see the PCIe driver in the device manager (Windows has detected the FPGA Board).

7. Executed the PCIE_DDR4.exe. Then in the menu putting the options 3, 4 and 5 gives the failure.

FYI: I have been using Quartus Prime Pro 18.1 in Windows 10.

Memory
Pcie

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  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Do you try the simulation tools ?

    Is it work for you ?


    Regards,

    Wincent_Intel


  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Wincent,

    I am still working on it and will update you. I am just curious that will you be available for a video meeting on tomorrow? Actually my colleague who is also working to debug have some questions. As he is in the USA, early morning singapore time will be good. Thank you.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Sorry I miss out your message. Maybe can you sent your question here ?

    then i can try to look at it before we have any meeting.


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Wincent,

    I really would like to have your help in debugging the design issue I am facing that is not resolved yet. After a week off, I just back to work, so sorry for the delay in response. I will post the result of the simulation of the design. Thank you very much.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Sijith,


    Any update on the simulation waveform ?


    Regards,

    Wincent_Intel


  • treble99's avatar
    treble99
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Wincent,

    I am also working with Sijith on this. I am trying to simulate the ep_g3x8_avmm256_integrated design in modelsim. I have referred to PCIe Solutions User Guide section 2.2 and am able to run the tcl script after some minor troubleshooting.

    I am able to view the waveform but I do not see much useful data there. I am not able drive the signals.

    I am currently referring to the second link i.e. modelsim quickstart.

    I will get back to you with some concrete questions soon.

    Thank you!

  • treble99's avatar
    treble99
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Wincent,

    I read through both documents but some things are still not clear. I also do not have experience in simulating BFMs before.

    1. I see a set of BFMs but How do i drive signals? I want to verify that data is being read and written to each DDR a and b.

    what should I add in The generated tcl script msim_setup.tcl

    2. I read the solution guide and it talks about receiving a successful message after `run -all`, I let it run for a really long time and I do not get any message and my log file is also empty.

    Attaching screenshots.

    Appreciate the help!

    Thank you,

    Manish

  • treble99's avatar
    treble99
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Wincent,

    Thank you for the link. I went through it. I also found this link to be helpful:

    https://community.intel.com/t5/Intel-Quartus-Prime-Software/Avalon-BFM-Test-Program/m-p/111682


    I understand the following. Please correct me if I am wrong.

    1. The BFMs need to be driven by another testbench program (different from setup tcl script). This would be a systemverilog .sv program.

    2. My reference design has several BFM provisions I can just drive the one I want.

    3. For the MUT instantiation, I found it under the generated tb file : `ep_g3x8_avmm256_integrated_tb/ep_g3x8_avmm256_integrated_tb/sim` This is one level above the mentor directory.


    I am now setting up my own test bench program and trying to get it to work.

    I will get back to you with more precise questions based on how it works.

    Thank you,
    Manish