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Altera_Forum's avatar
Altera_Forum
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16 years ago

Anyone using Altera PCIe core with Avalon-MM in SOPC?

Apologies for the acronym rich title :)

I'm having problems with an SOPC Builder design that uses the PCI Express Compiler core plus some home grown IP. The data transfer protocol linking the blocks is Avalon-MM. (Incidentally, I don't use a Nios processor).

The design compiles and works OK in Quartus 7.2, but I run into a Java "Null pointer exception" when generating the SOPC builder code under Quartus 8.1. This appears to be fixed in Quartus 9.0, but the compiled design now fails to work correctly in respect of system memory reads through the PCI Express core!

If any of this sounds familiar, or you are using the PCI Express core in a similar way, it would be great to compare notes!

Thanks ....

Greg

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I'm using the Avalon MM + Altera PCIe core. Before i'm compiling with Quartus 8.1, now i'm using the Quartus 9.0, but i'm not having this problem or messages like that.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi rodwill,

    Thanks for your reply. I'm trying to track down the cause of my problems, and it's extremely helpful if I know that someone else has been there before and knows that it can work :-)

    When you've got a second, could you let me know if your design uses the slave (Rx) port on the PCIe core, as this is where I have most problems.

    Many thanks,

    Greg
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes. My design uses the slave port, like the application note 532 (http://www.altera.com/literature/an/an532.pdf (http://www.altera.com/literature/an/an532.pdf)). The read and write master ports of the DMA Controller are connected with Rx Slave port of PCIe Core. When the dma controller generate read or write request, this ones generates PCIE Mem read or write requests packets.

    Take a look in Avalon-MM-to-PCI Express Address Translation Section in the Chapter 4 of PCI Express User Guide. It's very important to understand the Address Translation. It's important too verify your host software and driver. Because when you generate a write request in slave Rx Port, this request will be translated and will generate a PCIe Mem Write Packet. This packet will write the data in the address translated and may cause memory write in protected regions of the host memory (take a look at the driver jungo and the function of Dma Lock, which reserves a physical memory area for safe write or read by the pci express link).
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi all!

    I'm new to SOPC builder generated systems and I have some question (maybe, it is related to the problem discussed above...)

    The design is based on ArriaGX kit.

    I've defined PCIe core + DMA controller + some custom module as Avalon slave, using SOPC builder.

    And using Jungo evaluation software as debug tool (writing / reading to the PCIe device).

    (pls, see screenshots for connections)

    http://www.ee.bgu.ac.il/~andreylu/1.PNG

    I do see write transactions to the Avalon-slave (s0), from PC to the device. but i cannot perform read from the slave module.

    The module does not use waitrequest and has the simplest avalon-slave interface.

    More than that, Jungo application cannot access the card after unsuccesful reading, only SOF reprograming and rescan system devices afterwards helps.

    Does anyone have an idea where to look for a problem?