Altpll_0: Port phasecounterselect has width 3 in TCL, but 34 in the design file

Question

Hi,

I'm using Cyclone 10 LP development kit, and I'm building a qsys in Quartus 18.1 prime lite version.

I use altpll intelFPGA IP in qsys, when I generate VHDL code for qsys, I get the error "Error : altpll_0: Port phasecounterselect has width 3 in TCL, but 4 in the design file".

I followed the following link to modify the altera_avalon_altpll_hw.tcl, but it does not solve the problem. I realized that the error is different from the one in the link which has 4 in TCL, but 3 in the design file. http://ftp.beckhoff.com/download/document/io/ethercat-development-products/ethercat_ipcore_datasheet_addendum_v2i5.pdf

Can anybody help me with this?

Thank you very much in advance!

Jasmine

vicky1 · Answer

Hi,Could you please check the below solution?https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd07202015_476.htmlplease let me know , how it works for you. Regards,Vicky

mingyuexin · Answer

Hi Vicky,

Thank you very much for the answer.

Actually I fixed it by myself by remove the altpll ip and add an new altpll ip again without changing altera_avalon_altpll_hw.tcl.

The reason could be that I copied the qsys from somewhere (either from my previous design for MAX or from an example design for cyclone 10 LP in an older Quartus version).

With best wishes

Jasmine.

vicky1 · Answer

Hi Jasmine,Glad to know that you could able to resolve the issue by yourself.Regards,Vicky

Forum Discussion

Altpll_0: Port phasecounterselect has width 3 in TCL, but 34 in the design file

3 Replies

Recent Discussions

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design