Altpll_0: Port phasecounterselect has width 3 in TCL, but 34 in the design file

Hi, I'm using Cyclone 10 LP development kit, and I'm building a qsys in Quartus 18.1 prime lite version. I use altpll intelFPGA IP in qsys, when I generate VHDL code for qsys, I get the error "Er...