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Mingyuexin
Occasional Contributor
Occasional ContributorAltpll_0: Port phasecounterselect has width 3 in TCL, but 34 in the design file
Hi, I'm using Cyclone 10 LP development kit, and I'm building a qsys in Quartus 18.1 prime lite version. I use altpll intelFPGA IP in qsys, when I generate VHDL code for qsys, I get the error "Er...
MingyuexinOccasional Contributor
Occasional ContributorHi Vicky,
Thank you very much for the answer.
Actually I fixed it by myself by remove the altpll ip and add an new altpll ip again without changing altera_avalon_altpll_hw.tcl.
The reason could be that I copied the qsys from somewhere (either from my previous design for MAX or from an example design for cyclone 10 LP in an older Quartus version).
With best wishes
Jasmine.
