ALTGX transceiver operates in Lock-to-Reference mode?

So basically, is the lock-to-reference mode just to allow the CDR to get close to the correct frequency before locking to the data? The transceiver is not intended to be used in lock-to-reference mode?

If your reference clock is in some constant frequency relationship with your data (like say, ref clk is 10% of the data frequency), then is it possible to use the transceiver in lock-to-reference? Then at least the sampling clock should be in sync with the incoming data. Although I'm not sure what would determine the sampling phase in that case.