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Honored Contributoraltclkctrl mux with 2 pll outputs as inputs
I have clk_a and clk_b from 2 pll outputs, and I want to mux them to clk_out with altclkctrl. but Q2 complaints that altclkctrl inputs " must be driven by 1 PLLs but is driven by 2 PLLs" . What can i...
Altera_ForumHonored Contributor
Honored Contributorglitch at switch over is not an issue if your switching is occasional. The main problem with clk gating is clk skew(delay) leading to hold time violations. This applies to registers inside FPGA. If your clk is for outside registers then tackle timing according to your clk/data transition at pins and further.
ASIC designers normally gate their clk and tackle timing accordingly.
