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Altera_Forum
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15 years ago

altclkctrl mux with 2 pll outputs as inputs

I have clk_a and clk_b from 2 pll outputs, and I want to mux them to clk_out with altclkctrl. but Q2 complaints that altclkctrl inputs " must be driven by 1 PLLs but is driven by 2 PLLs" . What can i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If I violated rule C101 (using a simple 2:1 mux), what's the harm of doing this? the clock glitch?

Is the glitch only happened on the switchover point? If so, can I avoid the glitch by sampling data several cycles after the switchover?