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Honored Contributor
Honored Contributoraltclkctrl mux with 2 pll outputs as inputs
I have clk_a and clk_b from 2 pll outputs, and I want to mux them to clk_out with altclkctrl. but Q2 complaints that altclkctrl inputs " must be driven by 1 PLLs but is driven by 2 PLLs" . What can i...
Altera_ForumHonored Contributor
Honored Contributortry use one PLL and remember that gating rules apply to internal fpga clk use. If your clks are only for outside world then you can gate them and manage your timing accordingly.
