Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe problem is that I can't choose the way of generating the clks, I 've to use 2 PLLs at the moment. I've no choice but to figure out a way to mux 2 pll outputs. I am currently using "assign clk_out=clk_sel==0?clk_a:clk_b;" but that's violating the C101 rule.