Forum Discussion
Honored Contributoralt3pram VS altsyncram
Hi,
I am trying to generate a 3 port RAM with 2 write ports and 1 read port. This seems to be impossible with the megawizard since: - alt3pram (3 port RAM) creates 1 write port and 2 read ports - altsyncram (2 port RAM) creates 2 read&write ports but I can't use that because I need 3 different addresses. Is there any way to do what I want ? I am using Quartus v8.0 and am targeting a Stratix II device.3 Replies
Altera_ForumI don't think this is technically possible on dedicated memory blocks.
Altera memory blocks are dual-port, they have a maximum of two addresses. The 3-PORT Ram (two read ports and one write port) works by duplicating the memory blocks. This give you the extra read port. However this is simply not possible for two write ports. You can implement what you want using LEs, no memory blocks, but there is no megawizard support. Otherwise you would need to restructure your logic so that a single write port is active on the same cycle.- Altera_Forum
Running a 2x clock works, when the clock rates aren't that fast. I've seen requests like this where all three ports won't ever be physically running at the same time, just three different things are accessing, so muxing in/out the control and data would work(but this often isn't possible). If you look in the handbook at the memory make-up, and as vjAlter said, there are only two addresses per memory block(and I think all FPGAs now work that way. It takes more silicon to get addresses/data in and out then the actual bits that make up the memory). If none of that works, you might have to do something more complex. (Like have two memories, both with the same read but written to from the other write, and then a third memory that stores who wrote to each location last, which would me used to determine who was read from last, or something like that...)
- Altera_Forum
OK, thanks for the quick replies.
I was expecting those kind of answers... I am going to cut the RAM in blocks since I know by design that both write ports won't access the same block at the same time. This way I can multiplex the write ports for each block. Thanks !
