alt3pram VS altsyncram

Running a 2x clock works, when the clock rates aren't that fast. I've seen requests like this where all three ports won't ever be physically running at the same time, just three different things are accessing, so muxing in/out the control and data would work(but this often isn't possible). If you look in the handbook at the memory make-up, and as vjAlter said, there are only two addresses per memory block(and I think all FPGAs now work that way. It takes more silicon to get addresses/data in and out then the actual bits that make up the memory). If none of that works, you might have to do something more complex. (Like have two memories, both with the same read but written to from the other write, and then a third memory that stores who wrote to each location last, which would me used to determine who was read from last, or something like that...)