alt_remap_uncached, alt_uncached_malloc?

I fixed the bug. It was unrelated to caching as it turns out. I am writing/reading with the DDR2 directly to/from hardware.

I was performing a number of separate reads in a row from different addresses in memory, but the sgdma was getting backed up, as the "wait for current read transfer to finish" function I implemented wasn't working. This somehow caused the sgdma module to reverse the order of the read transfers. My solution was changing them to sync read transfers instead of asynch read transfers.

Thanks for your help.