Forum Discussion
Altera_Forum
Honored Contributor
15 years agoIf I'm using a dma to write and another to read, so that hardware is doing both the writes and reads, then is the nios caching any data?
If so I guess I should perform a flush every time I initiate the read dma? I ask because it seems that large chunks, the size of a small display span in memory, seem to be offset in the ddr2 in some magical way. I've gone through my code a million times and I seem to be managing the memory pointers properly, so I know there is something going on behind the scenes. But the cache isn't very big, so it wouldn't be able to offset the memory by that much i wouldn't think. Thanks for the response.