New Contributoragilex7 serial lite avs interface signals
Hi,
I'm using Serial Lite on Agilex7 device. I dont understand the meaning of AVS signals below,
[7:0] channel: is this just pass through the serial lite to the recv side?
[4:0] empty: according to the spec, this indicate the number of non-valid words in the final burst. What is word, is one word equals to 8B? or 4B? or else? My design implement a 4 lane duplex FGT connection. The empty signal can size maximum 31 non-valid words in the final burst, this means how many non-valid bytes in the final burst?
[3:0] num_valid_bytes_eob: this indicate the number of valid bytes in the last words of final burst. As in my design, 256bit data width, little-endian, how does this signal work?
is_usr_cmd: is this just pass through the serial lite to the recv side?
Hi,
AVS is Avalon Streaming Signals.
You can go through this 5. Avalon® Streaming Interfaces (intel.com).
[7:0] channel: is this just pass through the serial lite to the recv side?
Check this 6.3. MAC Signals (intel.com) and 4.1.2.1. Start-of-burst CW (intel.com)
You have 2-seperate signals for tx and rx.
Number of Words (1 word = 64 bits). Please refer 4.1.2. Control Word (CW) Insertion (intel.com)
num_valid_bytes_eob - This is 3-bit signal not 4-bit. 4.1.2. Control Word (CW) Insertion (intel.com)
And these 3-bits are for 8bytes/64-bits.
You need to experiment it but my understanding is from 256 bits the last 64-bits you need to consider because this signal itself you can represent max 8bytes.
You have two signals one for TX and one for RX.
Please refer 6.3. MAC Signals (intel.com)
Hope this clarifies.
Thank you,
Kshitij Goel
