Agilex 7 R-Tile CXL Type-2 IP Hang with Incomplete CXL.cache Operations

Device: DK-DEV-AGI027RBES (Power Solution 2)

Software Version: Quartus Prime Pro 24.3

IP Core: CXL Type 2 Hard IP

Issue Description: 

We observed that the CXL Type-2 IP can hang when CXL.cache transactions remain incomplete under heavy workloads. Our design is based on the CXL Type-2 design example, with a delay unit inserted between the CXL IP and the DDR controller.

We ran Intel MLC bandwidth tests on the CXL device while monitoring host reachability using continuous ping. In the first experiment (Figure 1), the delay unit inserted a 10,000-cycle delay for each CXL.mem request, with no CXL.cache operations involved. In this case, ping latency increased from approximately 0.2 ms to 45 ms, but the system remained stable.

In the second experiment (Figure 2), we replaced the 10,000-cycle delay with a CXL.cache operation, which typically completes in around 300 cycles. Under this configuration, the system hung and ping indicated that the host became unreachable. We observed that the CXL.cache request was issued but never received a response, leading to the hang.

We would like to know if there is a known issue or recommended solution for handling incomplete CXL.cache operations in this scenario.