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sg05006's avatar
sg05006
Icon for New Contributor rankNew Contributor
4 months ago
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Agilex-7 FPGA PCIe PIPE_Direct mode

Hello. I'm currently using the Intel PIPE_Direct Mode and have a question about something I don't understand.

The Agilex-7 R-tile PCIe PHY is said to support the SerDes PIPE_Direct mode, so why is the Data Path width [63:0]?

According to the Intel PIPE Specification, when using a SerDes PHY, the 8b/10b or 128b/130b encoding is performed by the MAC and then passed to the PHY, and it states that the data width is not a power of 2.

Thank you.

Pcie
  • Wincent_Altera's avatar
    Wincent_Altera
    4 months ago

    Hi ,


    Hope my previous reply clarified your doubt, is there any further question ?


    Regards,

    Wincent_Altera


3 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi


    Based on my understanding pm the guide, The "data width is not a power of 2" in the PIPE spec is about the number of bits encoded/transmitted per symbol, not the bus width of the interface. typically a multiple of 8, to match register sizes and align with standard data buses.


    As for example as below.

    PCIe Gen Encoding PIPE Data Path (Typical)
    Gen1/2 8b/10b 8, 16, 32 bits/lane
    Gen3/4/5 128b/130b 32, 64 bits/lane


    Regards.

    Wincent_Altera


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi ,


    Hope my previous reply clarified your doubt, is there any further question ?


    Regards,

    Wincent_Altera


  • sg05006's avatar
    sg05006
    Icon for New Contributor rankNew Contributor
    4 months ago

    Thank you for the clarification. I understand now and have no further questions.

    Best regards,

    Sanghyun