Agilex 7 emif ip questions

Hello Frank,

The width of amm_address is heavily dependent on the external memory. Let's use an example to understand it:

Assuming I have a single rank DDR4 interface constructed using 16Gb x8 components, we can get the following information by referring to the DDR4 datasheet.

CS width = 1 (single rank)
Chip ID width = 0 (non-3DS device)
Bank Group width = 2 (from datasheet)
Bank Address width = 2 (from datasheet)
Row width = 17 (from datasheet)
Column width = 10 (from datasheet)

When we select the "CS-CID-Row-Bank-Col-BG" scheme in EMIF IP, the definition of amm_address would be:

amm_address[27:11] = Row[16:0]
amm_address[10:9] = Bank[1:0]
amm_address[8:2] = Column[9:3] (The lower 3 bits are omitted because DDR4 uses a 8n prefetch architecture)
amm_address[1:0] = BG[1:0]

The field "CS" is discarded because there is only one rank. There is no "CID" either as this is a non-3DS scenario.

Since the EMIF IP uses standard Avalon Memory Mapped interface, you may refer to the Avalon specification for the usage and waveforms.
Additionally, simulating an EMIF example design and viewing its waveform is also a good starting point.

Here are the timing diagrams in case you would need them now:

Thanks.