Forum Discussion
Agilex 5 GTS Direct PHY RX simplex cold start issue
Hello,
I have a design that instantiates the GTS Direct PHY in RX Simplex mode (1 lane). When the design is loaded from the configuration flash device, the PHY remains stuck in the “RX Data Loss / CDR Lock Loss (Auto-Recovery)” state indefinitely.
Below is a transitional-mode power-on capture (greater than 10 s):
And here is a zoomed-in view of the startup sequence showing the external resets:
When I download the same configuration as a .sof file, the receiver starts up normally — no lock-loss events are observed.
After rx_ready asserts, there are no further transitions, so the capture was stopped at that point.
Any insight or suggestions on what might cause this difference between .jic(flash) and .sof (volatile) configuration behavior would be greatly appreciated.
Thank you!
2 Replies
- AnonymousNot applicable
The toggling reset_ack after asserting reset is not expected. Also the rx_ready not stable.
Check with a generated example design to isolate if this design dependent.
Is this your own board or a devkit?- sa110
New Contributor
This is neither my own nor DevKit. It is iWave SOM. A5 GTS PHY examples do not cover the case with simplex RX and simplex TX on the separate channels of the same bank.