Honored ContributorHi, I am new to FPGA and programming. I have a simple....I thought it was, program where I want to have a 1nS pulse every 25Mhz. I am using the Cyclone V GX Starter Kit and believe I need to add the Altera PLL IP so I can get a faster clock so I can divide it down. When I create the PLL IP how do I add it to my existing code? Thanks Gregg
Honored ContributorHi,
Instantiate the PLL in your design file. If you are using VHDL/Verilog use port map to have a connection between the files. Chech how they have Instantiated the PLL IP in design. http://www.ece.ucdavis.edu/~bbaas/180b/tutorials/using.a.pll.pdf https://alteraforum.com/forum/showthread.php?t=32579 Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)Honored ContributorHi Anand, Thanks for the information. I ran the wizard, it was a little different from the ucdavis post but, it helped a lot. I now have it working! Thanks Gregg
