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Altera_Forum
Honored Contributor
Honored ContributorAdding Altera PLL IP to program
Hi, I am new to FPGA and programming. I have a simple....I thought it was, program where I want to have a 1nS pulse every 25Mhz. I am using the Cyclone V GX Starter Kit and believe I need to add the ...
Altera_ForumHonored Contributor
Honored ContributorHi,
Instantiate the PLL in your design file. If you are using VHDL/Verilog use port map to have a connection between the files. Chech how they have Instantiated the PLL IP in design. http://www.ece.ucdavis.edu/~bbaas/180b/tutorials/using.a.pll.pdf https://alteraforum.com/forum/showthread.php?t=32579 Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
