Adding Altera PLL IP to program

Hi,

Instantiate the PLL in your design file.

If you are using VHDL/Verilog use port map to have a connection between the files.

Chech how they have Instantiated the PLL IP in design.

http://www.ece.ucdavis.edu/~bbaas/180b/tutorials/using.a.pll.pdf

https://alteraforum.com/forum/showthread.php?t=32579

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)