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Altera_Forum's avatar
Altera_Forum
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15 years ago

aclr and sclr - difference

Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Setting the clock block's reset to active low means that the input reset to the DSP Builder system is expected to be low. DSP Builder will convert that reset to whatever is expected by its own internal blocks.