aclr and sclr - difference

I can not agree more with you. However, you do not answer my questions. This is DSP Builder Forum, therefore my questions are related to the DSP Builder Altera Blockset.

I was previously asking about a block called 'Clock Block' where one can set the aclr reset flank to active low/high. The question was, whether this setting has an influence on aclr input of other blocks. The second question was related to a block called ' Global Reset Block'.

To be even more clear I say it once more - I DO NOT have any problems with setup/hold/metastability violations. I was asking about DSP Builder Blockset behaviour bacause I was to lazy to check the generated vhdl files.

I hope this is clear now,

best regards