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Altera_Forum's avatar
Altera_Forum
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15 years ago

aclr and sclr - difference

Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanx, I'm not quite sure about the aclr though. I'm using the Clock Block (DSP Builder , Altera Blockset) where the aclr can be set to active low/high. So, I suppose that the logic of others Blocks will be adjusted to the setting from Clock Block accordingly. Can you confirm it ?

Also, to confuse me even more, there is a Global Reset Block ,called SCLR, described as follows 'Any signal driven by global reset gets connected to the asynchronous global reset circuitry'. If its asynchronous, why is it called SCLR then ? :)

Best Regards,

Joel