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Altera_Forum
Honored Contributor
Honored Contributoraclr and sclr - difference
Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_ForumHonored Contributor
Honored ContributorYes you should be able to - but remember that because aclr is immediate, the blocks with sclr will come out of reset 1 clock cycle later than the ones with aclr.
Aclr should follow the same rules. Internal logic is usually best kept as active high for ease of reading. Active high or low uses the same amount of current, unlike on inter-device connections on a PCB, that are usually active low, to reduce current draw.
