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Altera_Forum's avatar
Altera_Forum
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15 years ago

aclr and sclr - difference

Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok thanks, so I can use the same synchronous reset signal for aclr and sclr ports without any problems, right ?

In respect to the DSP Altera Blocks, the "sclr" is always positive flank reset (0->1), and what about aclr ? Is it negative or positive ?

Regards,

Joel