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Altera_Forum
Honored Contributor
Honored Contributoraclr and sclr - difference
Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_ForumHonored Contributor
Honored Contributoraclr = asynchronous clear. Registers are reset immediatly.
sclr = synchronous clear. Registered are reset on the next rising edge of the clock. using aclr can be dangerous if you dont control it properly. If you have to use aclr ports, its best to reset them from a synchronous source. Aclr can be useful in VHDL code for setting powerup values sclr is much safer (and recommended) but you cannot infer power up values from it.
