Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

aclr and sclr - difference

Hi, can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? Thanks ppl !
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

aclr = asynchronous clear. Registers are reset immediatly.

sclr = synchronous clear. Registered are reset on the next rising edge of the clock.

using aclr can be dangerous if you dont control it properly. If you have to use aclr ports, its best to reset them from a synchronous source. Aclr can be useful in VHDL code for setting powerup values

sclr is much safer (and recommended) but you cannot infer power up values from it.