Access AN639 Example Design files

I'm trying to download and look at the Design Examples from application note AN639 (Inferring Stratix DSP Blocks for FIR Filtering Applications). I can download the PAR files, but am not able to extract readable rtl (verilog or VHDL) from the files (using Quartus) following the steps on the webpage. Is there an alternative way I can access these files?

I registered for a premier account, and received an email saying I was accepted. I'm an engineer at BAE Systems Manassas VA.