About pll IP dynamic configuration of arria V can not success on board

Question

Hi all,

I face one problem, when I simulate the pll dynamic configuration, the pll can lock after modifying setting(M,N,C) through reconfigure ip wethere I reset pll or not. But when I on board test, the pll can not output the frequency which I want when I set the same setting as simulation, if i don't reset pll after modifying setting, it can not lock; When I reset one cycle, the pll can lock but it can not output correct frequency; When I reset many cycle, the pll will not output anything which looks like that it can not work when I release reset. The setting I think it's okay, because I find them at .mif file.

software: quartus ii 13.1

chip : arria V GXA7

PLL : fpll, work at interger model.

reference clock: 24Mhz (external osc).

Could someone can give me some advice?

Best regards,

Lambert

engwei_o_intel · Answer

Hi Lambert
Can we check on few things:
1. Is your external clock source cleaned? Before reconfiguration happened, is the PLL able to lock and produce correct output clock frequency?
2. What is the expected output and what is the output you obtained after reconfiguration?
3. Are you able to share your sample design together with the testbench?
Thanks.
Eng Wei

lambert_yu · Answer

Hi Eng Wei,
   For the question you care:
  1. external clock source is clean and pll can lock before reconfiguration;
  2. I want to get 12Mhz output, but the output is close to the 24Mhz ( it's almost the same with the output frequency before reconfiguration).
  3. Because of comfidentiality principle, I have no power to share the code, sorry. 
   Could you build one case, and see that you will get the same result?
Best regards,
Lambert

engwei_o_intel · Answer

Hi Lambert
there might be some issue with older version of Quartus:
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2017/are-there-any-known-issues-with-the-altera-pll-reconfig-ip-for-a.html

Are you able to move to newer version of Quartus? Also, can you check if you have post scale counter being cascaded? Cascading post scale counter will not work for reconfiguration.

Thanks.
Eng Wei

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About pll IP dynamic configuration of arria V can not success on board

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