Forum Discussion

lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
5 years ago

About pll IP dynamic configuration of arria V can not success on board

Hi all, I face one problem, when I simulate the pll dynamic configuration, the pll can lock after modifying setting(M,N,C) through reconfigure ip wethere I reset pll or not. But when I on board te...
lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
5 years ago

Hi Eng Wei,

For the question you care:

1. external clock source is clean and pll can lock before reconfiguration;

2. I want to get 12Mhz output, but the output is close to the 24Mhz ( it's almost the same with the output frequency before reconfiguration).

3. Because of comfidentiality principle, I have no power to share the code, sorry.

Could you build one case, and see that you will get the same result?

Best regards,

Lambert

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Lambert

there might be some issue with older version of Quartus:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2017/are-there-any-known-issues-with-the-altera-pll-reconfig-ip-for-a.html

Are you able to move to newer version of Quartus? Also, can you check if you have post scale counter being cascaded? Cascading post scale counter will not work for reconfiguration.

Thanks.

Eng Wei