ContributorAbout no service for the emif read request
Hi all,
Now I am debugging the EMIF IP (Master and Slave EMIF design) in my own custom design, before I have test the EMIF IP through the EMIF example design so I think there is no hardware issue, but there is problem when used this IP in my own custom design:
For some case( read and write request for EMIF ip is random, and read and write operation is sequential, and all requests generated are all timinged to the emif_usr_clk of master and is related to the avalon interface signals of master, all above requests are all stored into one async fifo, and slave will read these requests when its avalon_ready signal is high and async_fifo is not empty), but from the debug signals, I found that all read requests and write requests can be executed by the master, but for the slave EMIF, though it gots all the read requests, but for the few read requests, it didn't output related read data, is there bus contension problem or any other things which I have not notice? Or can I change the primitives of memory controller? Or do any other problems leads to this problem? Could someone give me some advices?
Brs,
Lambert
