Contributor
Regular ContributorHi Lambert,
Do you have any warning messages when you are compiling the design?
Do you check your data bus width of the Avalon master and EMIF IP Avalon slave?
Thanks,
Adzim
ContributorHi Adzim,
1) I make sure that there is no warning about EMIF IP after compile.
2) I make sure that the width is right.
Add some information:
for the write request, 2KB/(time*IP) (sequential), for the read request, 1KB/(time*IP)(sequential), I can not make sure that DDR will write/read the same bank, bank group.
Just for the above case,
If the sum of write data is (2KB*N+64B*2, 2KB*(N+1)) , 2KB@write request, 1KB@read request, there is no above phenomenon;
If the sum of write data is (2KB*N, 2KB * N + 64B *2) for every write request (if N = 1, I will need 2*write request to complete this write operation). And the sum of read data for every read request is 1KB, the above phenomenon will be appear after FPGA runs a short time(Read and write requests are interleaved).
1) I try to add tWTR or tRTW, tCCD, tRRD time, there is no effect for above phenomenon;
2) I try to add high-priority for all read requests and decremente the limite of the starvation);
3) Now I try to disable re-ordering, I will check is there effect?
Brs,
Lambert
