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Altera_Forum
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15 years ago

about CAS latency setting in ddr_hp_controller v.9.1

Hi, I have tried to generate full rate ddr_hp_controllerv.9.1 with clock frequency of 128mhz in stratixIII device. I noticed that Altera only support CL=3 for stratix III device. But the ddr da...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I have not worked with DDR, but I have worked with DDR2. My understanding is that the MAXIMUM frequency is limited by the CAS latency while the MINIMUM frequency is not influenced by CAS latency. The minimum frequency is determined by the DLL (not sure if DDR has DLL?). Therefore you can run your memory at 128MHz with a CL=3 if the memory device is specified to be able to run at 128MHz. Maybe at 128MHz you could have used CL=2.5 or CL=2, but if the core does not support it, you will have to live with a CL=3.

Regards,

Niki