A10 PCIe SR-IOV tag"... follow-on: Can tag/completion processing be moved to the Application Layer?

PPham3 had asked a question on his "A10 PCIe SR-IOV tag"... question about extended tag support, I don't see a way to ask a follow on so I'm asking it in a new question.

I understand that Intel has chosen to only support 64 of the possible 256 extended tags (that the PCIe spec supports, and other cores support). But, is there a way to configure the core to not process tags/completion-handling, i.e. move that processing to the application layer so that the user can support a full 256-tags?

In the FPGA Tools Forum I have a similar question:

Platform Designer - A10 PCIe SR-IOV core set for (3) PFs - do the PFs have to share the 64 extended non-posted tags, or does each PF get 64 tags?

In that one I mention that I see that the RTL generated when selecting Avalon-MM DMA supports 256 tags, and that the Intel DMA soft logic appears to manage those tags - and the HIP can be programmed to support 256 tags. So there appears to be a way to allow external support for managing more than the HIP's limitation: 64-tags. If so, how do you tell the HIP not to manage tags?