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RWitt's avatar
RWitt
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7 years ago

A10 PCIe SR-IOV tag"... follow-on: Can tag/completion processing be moved to the Application Layer?

PPham3 had asked a question on his "A10 PCIe SR-IOV tag"... question about extended tag support, I don't see a way to ask a follow on so I'm asking it in a new question. I understand that Intel has ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

Hie,

Please check my replies to your questions:

  1. But, is there a way to configure the core to not process tags/completion-handling, i.e. move that processing to the application layer so that the user can support a full 256-tags? My apologies, but no currently, there no method by Intel.

2. A10 PCIe SR-IOV core set for (3) PFs - do the PFs have to share the 64 extended non-posted tags, or does each PF get 64 tags? The PF's have to share the 64 extended non-posted tags.

3. In that one I mention that I see that the RTL generated when selecting Avalon-MM DMA supports 256 tags, and that the Intel DMA soft logic appears to manage those tags - and the HIP can be programmed to support 256 tags. So there appears to be a way to allow external support for managing more than the HIP's limitation: 64-tags. If so, how do you tell the HIP not to manage tags?

My apologies, but Intel does offer the option to configure HIP to manage tags

Regards,

Nathan