A different kind of embedded processor/controller

Are you going to implement CPU as a set of big LUTs?

Are there any practical results, comprasion suggested approach to conventional ones?

I have a preliminary bdf that I will try to attach later. It has 5 Trimatrix memory blocks, a few counters and some Mux/Regs. Also an alu and a couple of compares. Some of the memory is used essentially as a big LUT. Some memory for variable storage, stack, statements, and expressions. Most of the controls are done in memory microprogram which has been used in mainframe cpus. A C# program parses the C code and loads the memory blocks to do the function. The program also uses arrays and other objects to do an analog of the hardware for debugging. At present the stack can do arithmetic evaluation. I am still working on the microprogram analog.

Thanks for the question. I will work on getting more info up.

Hi all,

This idea is actually interesting and is not immediately obvious.

I believe you are suggesting that the fpga platform can be used as a fast software platform faster than Nios. Somewhere in between a DSP platform and fpga platform. This could be good say for cases where there is a too complex algorithmic processing that is tedious using HDL but easy in software and that doesn't need all the speed of fpga but demands more than the speed of nios.

Currently there are tools like C to HDL, or C to FPGA(without HDL), Matlab to HDL core generators, Labview to FPGA(without HDL)...etc. Some of them are meant for DSP software engineers to use fpgas directly. I believe adding Simknutt's idea is relatively viable option in this tool race.

Remember also that on the other end an FPGA can be used to hardwire all or a large number of a set of instructions leading to very fast custom computing machines.

kaz

Microsoft research did a study which I think is titled "Where's the beef", which found that a lot of time is spent doing instruction fetches when instructions and data share the same memory. The study was to compare FPGA to processor performance, I think for memory I think that any time that C code is compiled into a typical processor instruction set that there is time used to share resources. Just the fact that a value is fetched, tested, and then a decision is made forces serial operations. Parallel operations are key to performance.

Embedded memory blocks, each storing different kinds of information and operating in parallel will enhance performance. This design allows the fpga to be designed once and then use array data patterns to define the function. Since there are so many ways to use memory to handle the front end trigger signals, there will be cases when that portion of the FPGA would be redesigned. That would be analogous to attaching different peripherals to nios.

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Hi all,

This idea is actually interesting and is not immediately obvious.

I believe you are suggesting that the fpga platform can be used as a fast software platform faster than Nios. Somewhere in between a DSP platform and fpga platform. This could be good say for cases where there is a too complex algorithmic processing that is tedious using HDL but easy in software and that doesn't need all the speed of fpga but demands more than the speed of nios.

Currently there are tools like C to HDL, or C to FPGA(without HDL), Matlab to HDL core generators, Labview to FPGA(without HDL)...etc. Some of them are meant for DSP software engineers to use fpgas directly. I believe adding Simknutt's idea is relatively viable option in this tool race.

Remember also that on the other end an FPGA can be used to hardwire all or a large number of a set of instructions leading to very fast custom computing machines.

kaz

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Hi Mixa. A long ago I proposed a new kind of embedded processor, then kind of disappeared. It has been fun, but a lot of work and thought. Finally, I have a running testcase.

main()

{

if(x == 0)

if(x == 0) y = 2 + 3 * 4 - 4;

else y = 5;

while(x == 6)

{

x = x - 7;

}

for(x = 8; x < 9; x = x + 1)

{

y = 10;

}

}

This takes 51 clock intervals, assuming the multiply takes 1 cycle.

The for loop takes 36 for the 9 iterations while the if/assign takes 15.

Sorry that I forgot to respond to your question about the big LUTS. The cpu is a microprogrammed design that uses multi-port rams.

I don't know what comes next, It has taken a lot of time to get this far.