Forum Discussion
Altera_Forum
Honored Contributor
17 years agoMicrosoft research did a study which I think is titled "Where's the beef", which found that a lot of time is spent doing instruction fetches when instructions and data share the same memory. The study was to compare FPGA to processor performance, I think for memory I think that any time that C code is compiled into a typical processor instruction set that there is time used to share resources. Just the fact that a value is fetched, tested, and then a decision is made forces serial operations. Parallel operations are key to performance.
Embedded memory blocks, each storing different kinds of information and operating in parallel will enhance performance. This design allows the fpga to be designed once and then use array data patterns to define the function. Since there are so many ways to use memory to handle the front end trigger signals, there will be cases when that portion of the FPGA would be redesigned. That would be analogous to attaching different peripherals to nios.