Occasional Contributor
Super ContributorI reviewed the modified design with counter and fifo, but I can't even detect a valid data path from fifo to dma_wr_master. Data seems to run through ddr interface, although ddr is operated at a different clock. No idea why it's connected this way.
Occasional ContributorHi FvM,
Thank you very much for looking into the design. I am new to the hardware design and basically from a basic science background, so any suggestion to improve/correct the modified design design is highly appreciated (this is what I am looking for too).
The present design i have is on the basis of the my thought that the counter-FIFO data can be written directly to DDR4 memory without the intervention of DMA write (thought DMA write should involve if the transfer of data from the host computer to the DDR4-- in the example design where we create data in host computer and write it to DDR4). Please correct my understanding if it is not possible somehow in this case.
What I really want is stream the data generated in the counter (which on/off with an external switch) through a FIFO (Intel Avalon MM FIFO IP, with streaming input and MM-output that I have used) then the data should go to the PCIe DMA transfer example design and the data written in DDR4 element then should read from the host computer through API functions provided)
Any suggestion for this is highly appreciated.
