2S60 Demo Design that Came with DSP Builder

This definitely caused me (and my Altera FAE) alot of sleepless nights. I thought I would share what I learned with everyone here.

With version 7.0, it seems like there are some mistakes with the 2S60 demo design that came with DSP Builder.

If I just run the design as it is then ADC1 output is pure noise.

Mainly, this was due to the fact that the 2S60 board block from DSP Builder library had the wrong clock assignments. If you double click on the 2S60 block, the following parameters are set:

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• Clock Pin In: Pin_AM17

• Clock Pin Out (D2A_2_CLK): Pin_C16

• Clock Pin Out (D2A_1_CLK): Pin_B15

• Clock Pin Out: Pin_B18

• Clock Pin Out: Pin_C15

• Clock Pin Out (inverted): Pin_D16

• Clock Pin Out (inverted): Pin_D18

• Global Reset Pin: Pin_AG19

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However, in the board schematics, those pins actually refer to the following:

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• AM17 -> PLD_CLKIN0

• C16 -> DAC_PLLCLK2

• B15 -> DAC_PLLCLK1

• B18 -> ADC_PLLCLK1

• C15 -> DAC_PLLCLK1_N

• D16 -> DAC_PLLCLK2_N

• D18 -> ADC_PLLCLK2

• AG19 -> PLD_CLEAR_N

--- Quote End ---

It almost seems like some of the default clock settings were wrong. If everything were labeled properly, only four clocks would be needed, one to drive each output (2 ADCs and 2 DACs). Therefore, I changed it to the following:

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• Clock Pin In: Pin_AM17

• Clock Pin Out (D2A_2_CLK): Pin_C16

• Clock Pin Out (D2A_1_CLK): Pin_B15

• Clock Pin Out: Pin_D18

• Clock Pin Out: Pin_B18

• Clock Pin Out (inverted): None

• Clock Pin Out (inverted): None

• Global Reset Pin: Pin_AG19

--- Quote End ---

Another problem with the design is that in 7.0, the default DSP Builder DAC blocks do not have the proper pin assignments. An Altera AE got me the patch (which I have included below). To install the patch:

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• Close MATLAB/Simulink

• Place the attached files in the <Default DSP Builder root>/altlib (go ahead and replace the old files.

• Restart MATLAB/Simulink

• Replace the old DAC/ADC blocks with new ones from the DSP Builder library list.

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With the above two fixes, you should be able to get all four sine waves from all four channels (2 ADC and 2 DAC). However, the sine waves from the two ADC channel are a bit noisy (somewhat periodic noise). To get around that, I did the following:

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• Open up the automatically generated Quartus project.

• Expand the project architecture and double click on the PLL block to bring up the PLL megawizard GUI.

• Add an 180 degrees phase-shift to the output clock.

• Regenerate the PLL and recompile the Quartus project.

• Reprogram the board and re-run Signal Tap II.

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Voila! You should see clean sine waves from all four channels.