2S60 Demo Design that Came with DSP Builder

Hi Wimax,

Sorry for the late reply. For the last step, the steps are outlined below:

1. Start Analysis/Elaboration

2. Then in the entity window, expand the design

3. Once the design is expanded, you will see two instances of PLL

4. Double click the PLL instances to bring up the megawizard... make sure clock phase shift is set to 180 degrees (under output clocks). (I believe the PLL that you have to change is the first one: dspboard2S60_pll:uclklk_out2p).

5. Then recompille your design and it should work.

FYI... I think this issue has been fixed in 7.1, therefore it should not be a problem anymore...