Agilex 7 R-Tile CXL IP Support for QoS DevLoad and PCIe ATS

Device: DK-DEV-AGI027RBES (Power Solution 2)

Software Version: Quartus Prime Pro 24.3

IP Core: CXL Type-2 Hard IP

Issue Description

We have two questions regarding feature support in the Agilex 7 R-Tile CXL IP.

1. CXL QoS Device Load (DevLoad)

According to the CXL 2.0 Specification, Section 3.3.2 (QoS Telemetry for Memory), CXL.mem supports reporting QoS Device Load (DevLoad).

In the CXL IP example design, we observe that the DevLoad-related signal exists, but it is not actively used and appears to be statically tied to 0.

• Is CXL.mem QoS Device Load reporting supported in the current CXL Type-2 Hard IP?

• What is the expected host CPU behavior when DevLoad is asserted (e.g., bandwidth throttling, scheduling changes, or telemetry only)?

2. PCIe ATS (Address Translation Service) Requests

We would like to issue PCIe ATS requests to the host using the CXL.io interface.

• Does the Agilex 7 R-Tile CXL Type-2 Hard IP support generating PCIe ATS request packets?

• If supported, are there any specific configuration requirements or interface signals needed to enable ATS transactions through CXL.io?