Forum Discussion
RongY_altera
Contributor
3 hours agoHi,
1. CXL QoS Device Load (DevLoad)
As you've observed, the signal exists and it's tied to 0, and it is not connected to an internal telemetry engine. There is no further documentation describing dynamic generation or usage of this signal in the current UG.
2. PCIe ATS (Address Translation Service) Requests
Please check this link
https://community.altera.com/kb/knowledge-base/why-does-intel-agilex%C2%AE-7-r-tile-compute-express-link-cxl-1-12-0-fpga-ip-not-incl/342904
Thanks,
Rong