2S60 Demo Design that Came with DSP Builder

Hi wronghorizon,

Thanks for the much needed patches.

I'm not very sure how to perform the last step of adding a 180 degrees phase-shift to the output clock. In my generated Quartus project, I've just have three VHDL files, two for dspbuilder and one for the actual VHDL file. I cannot find the PLL block.

I'm also trying to assign pin for my separate Quartus block diagram so that I can have an equivalent Verilog file to compare against my dspbuilder project. Unfortunately in Quartus 7.0 there is NO pin_u14 for DAC A and pin_u15 for DAC B. I've checked with Quartus 6.0 but the pins are there. So I've changed the pins assignment to pin _B15 and pin_C16 in Quartus for DAC A and DAC B, respectively, as recommended in your dspbuilder example. Am I doing it correctly or do I need a separate patch for that.

Regards,

wimax